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| DG3157 New Product Vishay Siliconix High-Speed, Low rON, SPDT Analog Switch (2:1 Multiplexer/Demultiplexer Bus Switch) FEATURES D Direct Cross to Industry Standard SN74LVC1G3157 NC7SB3157, NLASB3175, Pl5A3157, and STG3157 D SC-70 6-Lead Package D 1.65-V to 5.5-V VCC Operation D 5-W Connection Between Ports D Minimal Propagation Delay D Break-Before-Make Switching D Zero Bounce In Flow-Through Mode DESCRIPTION The DG3157 is a high-speed single-pole double-throw, low power, TTL-Compatible bus switch. Using sub-micro CMOS technology, the DG3157 achieves low on-resistance and negligible propagation delay. The DG3157 can handle both analog and digital signals and permits signals with amplitudes of up to VCC to be transmitted in either direction. When the Select pin is low, B0 is connected to the output A pin. When the Select pin is high, B1 is connected to the output A pin. The path that is open will have a high-impedance state with respect to the output. Make-before-break is guaranteed. An eptiaxial layer prevents latch-up. FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION SC-70 6- Pin B1 GND B0 1 2 3 Top View Device Marking: G1 6 5 4 S V+ A TRUTH TABLE Logic Input (S) 0 1 Function B0 Connected to A B1 Connected to A ORDERING INFORMATION Temp Range -40 to 85C Package SC70-6 Part Number DG3157DL Document Number: 72648 S-32552--Rev. A, 15-Dec-03 www.vishay.com 1 DG3157 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Reference to GND V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 V S, A, Ba . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V+ + 0.3 V) Continuous Current (Any terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . "50 mA Peak Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "200 mA (Pulsed at 1 ms, 10% duty cycle) Storage Temperature (D Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C Power Dissipation (Packages)b 6-Pin SC70c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mW Notes: a. Signals on A, or B or S exceeding V+ will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC Board. c. Derate 3.1 mW/_C above 70_C New Product SPECIFICATIONS Test Conditions Otherwise Unless Specified Parameter DC Characteristics High Level Input Voltage VSH V+ = 1.65 to 1.95 V V+ = 2.3 to 5.5 V V+ = 1.65 to 1.95 V V+ = 2.3 to 5.5 V VBN = 0 V, IA = 30 mA V+ = 4.5 V VBN = 2.3 V, IA = -30 mA VBN = 4.5 V, IA = -30 mA V+ = 3 0 V 3.0 VBN = 0 V, IA = 24 mA VBN = 3.0 V, IA = -24 mA VBN = 0 V, IA = 8 mA VBN = 2.3 V, IA = -8 mA VBN = 0 V, IA = 4 mA VBN = 1.8 V, IA = -4 mA V+ = 4.5 V, IA = -30 mA On Resistance Fltaness RFLAT 0 < VBN < V+ V+ = 3.0 V, IA = -24 mA V+ = 2.3 V, IZ = -8 mA V+ = 1.65 V, IA = -4 mA V+ = 4.5 V, VBN = 3.15 V, IA = -30 mA On Resistance Matching Between Channels DRON V+ = 3.0 V, VBN = 2.1 V, IA = -24 mA V+ = 2.3 V, VBN = 1.6 V, IA = -8 mA V+ = 1.65 V, VBN = 1.15 V, IA = -4 mA Input Leakage Current IS IBN( ff) BN(off) IBN( ) BN(on) V+ = 5 5 V VA = 5 5 V 5.5 V, 5.5 V+ = 5 5 V VA/VB = 0 V/5 5 V 5.5 V, V/5.5 V+ = 5 5 V VA/VB = 0 V/5 5 V 5.5 V, V/5.5 Full Full Full Full Full Full Full Full Full Full Full Full Full Room Room Room Room Room Room Room Room Room Full Room Full Room Full -0.1 -1.0 -0.1 -1.0 -0.1 -1.0 6 6 9 8 12 9 13 12 18 6 12 22 90 0.32 0.31 0.30 0.29 0.1 -1.0 0.1 -1.0 0.1 -1.0 mA 0.75 V+ 0.7 V+ 0.25 V+ 0.3 V+ 7 12 15 9 20 12 30 20 50 W V Limits -40 to 85_C Symbol V+ = 3.0 V, VS = 0.25 V to 0.7 V+e Tempa Minb Typc Maxb Unit Low Level Input Voltage VSL On Resistance RON V+ = 2 3 V 2.3 V+ = 1 65 V 1.65 Off Stage Switch Leakage On State Switch Leakage Power Supply Power Supply Range Quiescent Supply Current V+ I+ V+ = 5 5 V VA = VB = V+ or GND 5.5 V, Full Room Full 1.8 5.5 1 10 mA www.vishay.com 2 Document Number: 72648 S-32552--Rev. A, 15-Dec-03 DG3157 New Product SPECIFICATIONS Test Conditions Otherwise Unless Specified Parameter Symbol V+ = 3.0 V, VS = 0.25 V to 0.7 V+e Vishay Siliconix Limits -40 to 85_C Tempa Full Full Full Full Room Full Room Full Room Full Room Full Room Full Room Full Room Full Room Full Full Full Full Full Minb Typc Maxb Unit AC Electrical Characteristice V+ =1.65 to 1.95 V Prop Delay Timef tPHL/tPLH VA = 0 V V+ =2.3 to 2.7 V V+ =3.0 to 3.6 V V+ =4.5 to 5.5 V V+ =1 65 to 1 95 V =1.65 1.95 1.2 0.8 0.3 10.2 10.4 5.9 6.2 4.1 4.5 2.6 2.9 10.2 10.4 5.9 6.2 4.1 4.5 2.6 2.9 0.5 0.5 0.5 0.5 7 3 pC ns V+ =2 3 to 2 7 V =2.3 2.7 Output Enable Timef tPZL/tPZH VLOAD = 2 x V+ for tPZL VLOAD = 0 V for tPZH V+ =3 0 to 3 6 V =3.0 3.6 V+ =4 5 to 5 5 V =4.5 5.5 V+ =1 65 to 1 95 V =1.65 1.95 V+ =2 3 to 2 7 V =2.3 2.7 Output Disable Timef tPLZ/tPHZ VLOAD = 2 x V+ for tPLZ VLOAD = 0 V for tPHZ V+ =3 0 to 3 6 V =3.0 3.6 V+ =4 5 to 5 5 V =4.5 5.5 V+ =1.65 to 1.95 V Break-Before-Make Break Before Make Timed tBBM V+ =2.3 to 2.7 V V+ =3.0 to 3.65 V V+ =4.5 to 5.5 V Charge Injectiond Q CL = 0.1 nF, VGEN = 0 V RGEN = 0 W V+ = 5 V V+ = 3.3 V Room Room Analog Switch Characteristics Off Isolationd Crosstalkd -3-db Bandwidthd OIRR XTALK BW RL = 50 W f = 10 MHz W, RL = 50 W Room Room Room -57.6 -58.7 u250 dB MHz Capacitance Control Pin Capacitanced B Port Off Capacitanced A Port Capacitance When Switch Enabled Notes: a. b. c. d. e. f. Room = 25C, Full = as determined by the operating suffix. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. Typical values are for design aid only, not guaranteed nor subject to production testing. Guarantee by design, nor subjected to production test. VIN = input voltage to perform proper function. Guaranteed by design and not production tested. The bus switch propagation delay is a function of the RC time constant contributed by the on-resistance and the specified load capacitance with an ideal voltage source (zero output impedance) driving the switch. www.vishay.com CIN CIO-B CIO-A(on) V+ = 5 V V+ = 0 V Room Room Room 4.9 t6.5 t18.5 pF Document Number: 72648 S-32552--Rev. A, 15-Dec-03 3 DG3157 Vishay Siliconix LOGIC DIAGRAM (POSITIVE LOGIC) New Product B 1 S 6 4 A B 3 Figure 1. TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) rON vs. VA vs. VCC 40 35 rON - On Resistance (W) 30 25 20 15 10 5 0 0.0 V+ = 2.3 V, IS = 8 mA V+ = 3.0 V, IS = 24 mA V+ = 4.5 V, IS = 30 mA V+ = 1.65 V, IS = 4 mA 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VA (V) www.vishay.com 4 Document Number: 72648 S-32552--Rev. A, 15-Dec-03 DG3157 New Product AC LOADING AND WAVEFORMS Vishay Siliconix VLD RL 500 W SW Open GND From Output Under Test CL 50 pF TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH SW Open RL 500 W VLD GND Load Circuit Figure 2. AC Test Circuit tr = 2.5 ns 90% Switch Input 10% tw tPLH tPHL 1.5 V 90% 1.5 V tf = 2.5 ns tf = 2.5 ns 3.0 V Logic Input 90% 1.5 V 10% 10% tr = 2.5 ns 90% 1.5 V GND tPLZ VLD 2 3.0 V 10% GND tPZL VOH Output 1.5 V 1.5 V Output Waveform 1 SW at VLD tPZH 1.5 V VOL + 0.3 V VOL tPHZ VOH VOH -0.3 V VOL Output Waveform 2 SW at GND Propagation Delay Times 1.5 V 0V Enable and Disable Time--Low- and High-Level Enabling Figure 3. AC Waveforms Notes: a. b. c. d. e. f. g. h. i. CL includes probe and jig capacitance. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 W. The outputs are measured one at a time with one transition per measurement. tPLZ and tPHZ are the same as tdis. tPZL and tPZH are the same as tdis. tPLH and tPHL are the same as tdis. VLD = 2 V+. Document Number: 72648 S-32552--Rev. A, 15-Dec-03 www.vishay.com 5 DG3157 Vishay Siliconix TEST CIRCUITS V+ Logic Input COM VO RL 50 W GND CL 35 pF VIN H New Product V+ VNO VNC NO NC IN tr <5 ns tf <5 ns VINL VNC = VNO VO Switch 0V Output 90% tD tD CL (includes fixture and stray capacitance) Figure 4. Break-Before-Make Interval V+ Rgen + Vgen VIN = 0 - V+ V+ NC or NO IN GND COM VOUT CL = 1 nF VOUT IN DVOUT On Off Q = DVOUT x CL On IN depends on switch configuration: input polarity determined by sense of switch. Figure 5. Charge Injection V+ 10 nF V+ NC or NO IN COM COM 0V, 2.4 V IN 10 nF V+ V+ COM Meter 0 V, 2.4 V GND GND HP4192A Impedance Analyzer or Equivalent f = 1 MHz RL Analyzer NC or NO V COM Off Isolation + 20 log V NO NC Figure 6. Off-Isolation www.vishay.com Figure 7. Channel Off/On Capacitance Document Number: 72648 S-32552--Rev. A, 15-Dec-03 6 |
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